The present invention concerns transmission of data within a computing system and pertains particularly to dynamic allocation and re-allocation of buffers in links of chained direct memory access operations.
A design demanding multiple concurrent chained direct memory access (DMA) operations can be limited in the number of concurrent chained-DMA operations which can be performed due to associated memory limits. For example, when each DMA operation is associated with a memory buffer, the memory buffers are typically allocated before the multiple concurrent chained-DMA operation is started so that each buffer can be linked to the chain. Once the chained-DMA operation has completed, all the buffers in the chain can be moved to the next stage in processing and eventually become free for re-use. During the time that the chained-DMA operation is in effect these buffers can not be used for other purposes. Thus, the number of concurrent chained-DMA operations is limited in a direct relationship to how much memory is available (and limited by that memory already utilized for purposes including other active chained-DMA operations). This problem is most prominent when there is a dynamic demand of the system to concurrently provide combinations of many (unrelated) data transfers, and each data transfers is relatively large. Concurrence is limited because of a lack of memory and/or the number of concurrent requests supported (and possibly other resource constraints).
One approach to the problem of concurrent demand of memory is to require more memory in the system. This is an expensive solution for many applications.
Another approach is to divide each multiple concurrent chained-DMA operation into smaller (in memory requirements) multiple concurrent chained-DMA operations and perform the overall data transfer in more, "smaller", re-usable multiple concurrent chained-DMA operation. One problem with this approach is that performance is typically poorer with more multiple concurrent chained-DMA operations because of the increased DMA control management associated with building, launching, and servicing completion of each chained-DMA operation. Additionally, performance may be lost during the gaps of time between one chained DMA operation being finished and another starting, unless complexity and components are added to the application to keep the data moving between chained DMA operations.
One application in which multiple concurrent chained DMA operations are used is within a Small Computer Systems Interface (SCSI) protocol bridge. A SCSI protocol bridge is a device which manages SCSI processes between a computer and associated SCSI target devices.
A disk array connected to a SCSI bus may take a computer request for 2.sup.20 bytes of data and separate this into 16 (2.sup.4) separate sub-requests for data to its underlying disk drives (each sub-request has 2.sup.16 bytes of data). When handling such a transfer within a SCSI protocol bridge using multiple concurrent chained-DMA operation, the limit on the number of concurrent data transfers is directly related to the amount of buffer memory available, and the sum of the data required for each concurrent sub-request.
The disk array may orchestrate queuing read-ahead requests to underlying drives at the launching of the first sub-request (and at each completion of a sub-request) in order to attempt to recover the gap in time that would otherwise occur if the sub-requests were serialized. However, this approach adds significant complexity. The problem in current designs is that memory used to buffer data for active (enabled, but not yet completed) chained-DMA operations is temporally poorly utilized when the application is such that the time between enabling the multiple concurrent chained-DMA operation and the completion of the multiple concurrent chained-DMA operation is typically much longer in time than any given associated memory buffer needs to be available for the operation and subsequent processing. Buffer memory for the entire operation is typically dedicated to the request for the entire time from "start" to "stop".